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Si4320
Bit 1: < ff >
Bit 0: < fe >
Enables FIFO fill after synchron word reception. FIFO fill stops when this bit is cleared.
Enables the 16bit deep FIFO mode. To clear the FIFO’s counter and content, it has to be set zero.
Note:
To restart the synchron word reception, bit 1 should be cleared and set. This action will initialize the FIFO and clear its content.
Bit 0 modifies the function of pin 6 and pin 7. Pin 6 (nFFS) will become input if fe is set to 1. If the chip is used in FIFO mode,
do not allow this to be a floating input.
11. Reset Mode Command
bit
15
1
14
1
13
0
12
1
11
1
10
0
9
1
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
dr
POR
DA00h
Bit 0 ( dr ): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For
more detailed description see the Reset modes section.
12. Status Read Command
bit
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
--
The read command starts with a zero, whereas all other control commands start with a one. Therefore, after receiving the first bit of the
control command the Si4320 identifies it as a read command. So as the first bit of the command is received, the receiver starts to clock out
the status bits on the SDO output as follows:
Status Register Read Sequence with FIFO Read Example
It is possible to read out the content of the FIFO after the reading of the status bits. The command can be aborted after any read bits by
rising edge of the select signal.
Note: The FIFO IT bit behaves like a status bit, but generates nIRQ pulse if active. To check whether there is a sufficient amount of data in
the FIFO, the SDO output can be tested. In extreme speed critical applications, it can be useful to read only the first four bits ( FIFO IT - LBD )
to clear the FFOV, WK-UP, and LBD bits. During the FIFO access the f SCK cannot be higher than f ref /4, where f ref is the crystal oscillator
frequency. If the FIFO is read in this mode the nFFS input must be connected to logic high level.
Definitions of the bits in the above timing diagram:
FIFO IT
FFOV
WK-UP
LBD
FFEM
DRSSI
DQD
CRL
ATGL
ASAME
OFFS6, 4-0
Number of the data bits in the FIFO is reached the preprogrammed limit
FIFO overflow
Wake-up timer overflow
Low battery detect, the power supply voltage is below the preprogrammed limit
FIFO is empty
The strength of the incoming signal is above the preprogrammed limit
Data Quality Detector detected a good quality signal
Clock recovery lock
Toggling in each AFC cycle
AFC stabilized (measured twice the same offset value)
Offset value to be added to the value of the Frequency control word
18
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